1. Field of the Invention
The present invention relates to a biasing scheme that mitigates the MOSFET body effect and reduces the effect of the well-to-substrate capacitance on the MOSFET. More specifically, the present invention, at high frequencies, mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET, and reduces the power consumed by the gain boosting amplifier.
2. Background Art
Operational amplifiers used in precision switched capacitor circuits are faced with very stringent requirements for their settling behavior and their dc performance. These requirements are particularly important when they are used in high speed, high resolution analog-to-digital converters such as those described in A. M. Marques et al., xe2x80x9cA 15b resolution Delta Sigma ADC in a lum CMOS technologyxe2x80x9d, IEEE Journal of Solid State Circuits, pp. 1065-75, July 1998; and Yves Geerts et al., xe2x80x9cA 3.3V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL applicationsxe2x80x9d, IEEE Journal of Solid State Circuits, pp. 927-36, July 1999. Often for such applications, the operational amplifiers use a gain boosted folded cascode topology because it can support high gain at wide bandwidths.
FIG. 1 is a schematic diagram of an exemplary conventional gain boosted folded cascode operational amplifier 100. The principles underlying the discussion in relation to FIG. 1 are not intended to be limited to the particular topology of operational amplifier 100.
In FIG. 1, operational amplifier 100 comprises a first active load leg 102 and a second active load leg 104 connected in parallel between a supply voltage xe2x80x9cVDDxe2x80x9d 106 and an analog ground xe2x80x9cVAGxe2x80x9d 108. (The skilled artisan would appreciate that, alternatively, a second supply voltage xe2x80x9cVSSxe2x80x9d could be used in place of VAG 108.) First active load leg 102 comprises a cascoded series of PMOSFETs xe2x80x9cM1xe2x80x9d 110 and xe2x80x9cM3xe2x80x9d 112; and a cascoded series of NMOSFETs xe2x80x9cM5xe2x80x9d 114 and xe2x80x9cM7xe2x80x9d 116. Second active load leg 104 comprises a cascoded series of PMOSFETs xe2x80x9cM2xe2x80x9d 118 and xe2x80x9cM4xe2x80x9d 120; and a cascoded series of NMOSFETs xe2x80x9cM6xe2x80x9d 122 and xe2x80x9cM8xe2x80x9d 124.
The gate terminals of M1 110 and M2 118 are together connected to a first bias voltage xe2x80x9cVBPxe2x80x9d 126 to hold the MOSFETs in saturation. The source terminal of M3 112 is connected to the inverting terminal of a gain boosting amplifier xe2x80x9cA1xe2x80x9d 128, while the output of A1 128 is connected to the gate terminal of M3 112 such that a feedback network xe2x80x9cFN1xe2x80x9d 130 is established. The source terminal of M4 120 is connected to the inverting terminal of a gain boosting amplifier xe2x80x9cA2xe2x80x9d 132, while the output of A2 132 is connected to the gate terminal of M4 120 such that a feedback network xe2x80x9cFN2xe2x80x9d 134 is established. The noninverting terminals of A1 128 and A2 132 are together connected to a second bias voltage xe2x80x9cVPREFxe2x80x9d 136 to hold the corresponding MOSFETs (i.e., M3 112 and M4 120) in saturation.
The source terminal of M5 114 is connected to the inverting terminal of a gain boosting amplifier xe2x80x9cA3xe2x80x9d 138, while the output of A3 138 is connected to the gate terminal of M5 114 such that a feedback network xe2x80x9cFN3xe2x80x9d 140 is established. The source terminal of M6 122 is connected to the inverting terminal of a gain boosting amplifier xe2x80x9cA4xe2x80x9d 142, while the output of A4 142 is connected to the gate terminal of M4 122 such that a feedback network xe2x80x9cFN4xe2x80x9d 144 is established. The noninverting terminals of A3 138 and A4 142 are together connected to a third bias voltage xe2x80x9cVNREFxe2x80x9d 146 to hold the corresponding MOSFETs (i.e., M5 114 and M6 122) in saturation. The gate terminals of M7 116 and M8 124 are together connected to a fourth bias voltage xe2x80x9cVBNxe2x80x9d 148 to hold the MOSFETs in saturation.
Each feedback network (e.g., FN1 130, FN2 134, FN3 140, or FN4 144), acts to hold the voltage at the source terminal of its driven MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122) equal to the bias voltage (e.g., VPREF 136 or VNREF 146) applied to the noninverting terminal of the corresponding gain boosting amplifier (e.g., A1 128, A2 132, A3 138, or A4 142). For example, A1 128 detects any difference in voltage between the source terminal of M3 112 and VPREF 136, and drives the voltage at the gate terminal of M3 112 to eliminate the difference.
Operational amplifier 100 further comprises a differential amplifier 150. Differential amplifier 150 comprises a current source xe2x80x9cITAILxe2x80x9d 152, a first amplifying PMOSFET xe2x80x9cM9xe2x80x9d 154, and a second amplifying PMOSFET xe2x80x9cM10 xe2x80x9d 156. The source terminals of M9 154 and M10 156 are connected together in parallel. ITAIL 152 is connected between VDD 106 and the source terminals of M9 154 and M10 156. The drain terminal of M9 154 is connected to the drain terminal of M7 116. The drain terminal of M10 156 is connected to the drain terminal of M8 124. M9 154 and M10 156 comprise a differential pair and act to control the distribution of current flowing from ITAIL 152 between VDD 106 and VAG 108. The sum of the current flowing through both M9 154 and M10 156 equals ITAIL 152.
Operational amplifier 100 receives a differential input signal and produces a differential output signal. The differential input signal comprises a positive input signal xe2x80x9cVin+xe2x80x9d 158 and a negative input signal xe2x80x9cVinxe2x88x92xe2x80x9d 160. Vin+158 is received at the gate terminal of M9 154. Vinxe2x88x92160 is received at the gate terminal of M10 156. The differential output signal comprises a positive output signal xe2x80x9cVout+xe2x80x9d 162 and a negative output signal xe2x80x9cVoutxe2x88x92xe2x80x9d 164. Vout+162 is presented at the drain terminal of M5 114. Voutxe2x88x92 164 is presented at the drain terminal of M6 122.
So, for example, as Vin+158 rises with respect to Vinxe2x88x92 160, the portion of the total current of ITAIL 152 that flows through M9 154 (i.e., a PMOSFET) and M7 116 becomes smaller, while the portion that flows through M10 156 and M8 124 becomes larger. With the gate-to-source voltages of M7 116 and M8 124 (i.e., NMOSFETs) held equal to VBN 148, the decreased amount of current flowing through M7 116 causes its drain-to-source voltage to decrease, while the increased amount of current flowing through M8 124 causes its drain-to-source voltage to increase. Because the source terminal of M7 116 is connected to VAG 108, the decrease in its drain-to-source voltage is realized as a lower voltage at its drain terminal. Likewise, because the source terminal of M8 124 is connected to VAG 108, the increase in its drain-to-source voltage is realized as a higher voltage at its drain terminal. So, in first active load leg 102, there is a larger drop in voltage potential between VDD 106 and the drain terminal of M7 116, while in second active load leg 104, there is a smaller drop in voltage potential between VDD 106 and the drain terminal of M8 124. Initially, this causes less current to flow through first active load leg 102 and more current to flow through second active load leg 104. However, the MOSFETs in these legs strive to maintain the current flowing through them at a constant level.
As the drain terminal of M7 116 is connected to the source terminal of M5 114, the voltage at the source terminal of M5 114 also falls so that the gate-to-source voltage of M5 114 increases. Because the current flowing through M5 114 strives to remain constant, the increase in the gate-to-source voltage of M5 114 (i.e., a NMOSFET) causes a decrease in its drain-to-source voltage of a larger magnitude than the increase in the gate-to-source voltage. Via FN3 140, this effect is enhanced by A3 138, which receives the lower voltage at the source terminal of M5 114, inverts it, amplifies it, and applies it to the gate terminal of M5 114 causing the increase in the gate-to-source voltage to be larger than it would be in the absence of A3 138. Consequently, the decrease in the drain-to-source voltage of M5 114 is also larger than it would be in the absence of A3 138. Because FN3 140 acts to hold the voltage at the source terminal of M5 114 equal to VNREF 146, the decrease in the drain-to-source voltage of M5 114 is realized as a lower voltage at its drain terminal.
With the source-to-gate voltage of M1 110 held equal to the difference between VDD 106 and VBP 126, the initial decrease in the amount of current flowing through M1 110 (i.e., a PMOSFET) causes its source-to-drain voltage to increase. Because the source terminal of M1 110 is connected to VDD 106, the increase in its source-to-drain voltage is realized as a lower voltage at its drain terminal. As the drain terminal of M1 110 is connected to the source terminal of M3 112, the voltage at the source terminal of M3 112 also falls so that the source-to-gate voltage of M3 112 decreases. Because the current flowing through M3 112 strives to remain constant, the decrease in the source-to-gate voltage of M3 112 (i.e., a PMOSFET) causes an increase in its source-to-drain voltage of a larger magnitude than the decrease in the source-to-gate voltage. Via FN1 130, this effect is enhanced by A1 128, which receives the lower voltage at the source terminal of M3 112, inverts it, amplifies it, and applies it to the gate terminal of M3 112 causing the decrease in the source-to-gate voltage to be larger than it would be in the absence of A1 128. Consequently, the increase in the source-to-drain voltage of M3 112 is also larger than it would be in the absence of A1 128. Because FN1 130 acts to hold the voltage at the source terminal of M3 112 equal to VPREF 136, the increase in the source-to-drain voltage of M3 112 is realized as a lower voltage at its drain terminal.
Thus, the changes in the drain-to-source voltage of M3 112 and the source-to-drain voltage of M5 114 act to decrease the voltage at Voutxe2x88x92164. Through a similar but converse process, changes in the drain-to-source voltage of M4 120 and the source-to-drain voltage of M6 122 act to increase the voltage at Vout+162. In this manner, operational amplifier 100 acts to amplify the rise at Vin+158 with respect to Vinxe2x88x92160.
However, the overall settling behavior of operational amplifier 100 can be limited by the parameters of its gain boosting amplifiers (i.e., A1 128, A2 132, A3 138, and A4 142). For example, the gain boosting amplifiers normally require wider bandwidths than does operational amplifier 100 itself. This characteristic is explained in Klaas Bult et al., xe2x80x9cA Fast Settling CMOS opamp for SC Circuits with 90-dB DC gainxe2x80x9d, IEEE Journal of Solid State Circuits, pp. 1379-84, December 1990. Furthermore, the settling performance requirements specifically needed for precision switched capacitor circuits dictate that the gain boosting amplifiers must have fairly high levels of gain and fast settling performances. (For this reason, the gain boosting amplifiers themselves often employ a folded cascode topology.) These requirements essentially necessitate that the MOSFETs within gain boosted operational amplifier 100 be characterized by relatively large capacitive values. Therefore, each gain boosting amplifier (e.g., A1 128, A2 132, A3 138, or A4 142) must drive a relatively large MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122). Unfortunately, physical parameters internal to these MOSFETs can give rise to limitations in the functioning of gain boosted operational amplifier 100.
Under conventional methods for fabricating MOSFETs on integrated circuit chips, both PMOSFETs and NMOSFETs are fabricated on the same chip. Typically, a positively doped semiconductor substrate is used for the chip. Therefore, fabrication of PMOSFETs necessitates the formation of negatively doped semiconductor wells embedded within the positively doped semiconductor substrate. Each negatively doped well comprises a body for a PMOSFET.
FIG. 2A is a cutaway, cross sectional view of a conventionally fabricated PMOSFET 200. The skilled artisan would recognize that PMOSFET 200 comprises a positively doped semiconductor substrate 202. Embedded within substrate 202 is a negatively doped semiconductor well 204. Embedded within well 204 are a first positively doped region 206 and a second positively doped region 208. First and second regions 206, 208 are separated within well 204 by a channel 210. The measure of separation is referred as channel length xe2x80x9cLxe2x80x9d. Additionally, channel 210 has a width xe2x80x9cWxe2x80x9d (not shown) perpendicular to the plane of FIG. 2A. The ratio W/L is referred to as a xe2x80x9cchannel constantxe2x80x9d. A metal oxide layer 212 is deposited onto well 204 and partially covers first and second regions 206, 208. A metal is deposited onto metal oxide layer 212 opposite channel 210 to form a gate terminal 214 for PMOSFET 200. The metal is also deposited opposite region 206 to form a source terminal 216, opposite region 208 to form a drain terminal 218, and opposite well 204 to form a body terminal 220 for PMOSFET 200.
FIG. 2B is a schematic diagram of a small signal model circuit 250 of PMOSFET 200. Circuit 250 comprises five nodes corresponding to gate terminal 214, source terminal 216, drain terminal 218, body terminal 220, and a xe2x80x9csubstratexe2x80x9d node 252. Typically, substrate 252 is connected to VAG 108. A resistor xe2x80x9cr0xe2x80x9d 254 is connected between source and drain terminals 216, 218.
Resistor r0 254 models the value of the output resistance of PMOSFET 200. A capacitor xe2x80x9cCgs 256 is connected between gate and source terminals 214,216; a capacitor xe2x80x9cCgdxe2x80x9d 258 is connected between gate and drain terminals 214, 218; a capacitor xe2x80x9cCgbxe2x80x9d 260 is connected between gate and body terminals 214, 220; a capacitor xe2x80x9cCsbxe2x80x9d 262 is connected between source and body terminals 216, 220; a capacitor xe2x80x9cCdbxe2x80x9d 264 is connected between drain and body terminals 218, 220; and a capacitor xe2x80x9cCwellxe2x80x9d 266 is connected between body terminal 220 and substrate 252. The capacitors model the values of the capacitances between regions within PMOSFET 200.
Two current sources are connected in parallel between source and drain terminals 216,218: a first current source xe2x80x9cigxe2x80x9d 268 and a second current source xe2x80x9cibxe2x80x9d 270. ig 268 models the current producing behavior of PMOSFET 200 due to the small signal voltage potential between gate and source terminals 214, 216. ib 270 models the current producing behavior of PMOSFET 200 due to the small signal voltage potential between body and source terminals 220, 216.
The value of ig 268 can be expressed as shown in Eq. (1):
ig=gmvgs,xe2x80x83xe2x80x83Eq. (1) 
where xe2x80x9cvgsxe2x80x9d is the small signal voltage potential between gate and source terminals 214, 216, and xe2x80x9cgmxe2x80x9d is the transconductance due to vgs (i.e., gate transconductance). gm is defined as shown in Eq. (2):
gm=xcex94ID/xcex94VGS,xe2x80x83xe2x80x83Eq. (2) 
where xe2x80x9cxcex94IDxe2x80x9d is the change in the large signal current passing through drain terminal 218 and xe2x80x9cxcex94VGSxe2x80x9d is the change in the large signal voltage potential between gate and source terminals 214, 216.
The value of ib 270 can be expressed as shown in Eq. (3):
ib=gmbvbs,xe2x80x83xe2x80x83Eq. (3) 
where xe2x80x9cvbsxe2x80x9d is the small signal voltage potential between body and source terminals 220, 216, and xe2x80x9cgmbxe2x80x9d is the transconductance due to vbs (i.e., body transconductance). gmb is defined as shown in Eq. (4):
gmb=xcex94ID/xcex94VBS,xe2x80x83xe2x80x83Eq. (4) 
where xe2x80x9cxcex94VBSxe2x80x9d is the change in the large signal voltage potential between body and source terminals 220, 216.
Often, Cgb 260 has a negligible value so that a gate capacitance xe2x80x9cCgxe2x80x9d (i.e., between gate terminal 214 and the remaining elements of small signal model circuit 250) can be expressed as shown in Eq. (5):
Cg=Cgs+Cgd.xe2x80x83xe2x80x83Eq. (5) 
As can be observed from FIG. 1, in a conventional gain boosted folded cascode topology, each driven MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122) is usually connected in series with another (non-driven) MOSFET (e.g., M1 110, M2 118, M7 116, or M8 124), such that the source terminal of the driven MOSFET is connected to the drain terminal of the non-driven MOSFET (i.e., the MOSFETs are cascoded). In this configuration, the two MOSFETs form a source follower, with an input signal driving the gate terminal of the driven MOSFET, an output signal produced at the source terminal of the driven MOSFET, and a current source provided by the non-driven MOSFET.
For example, in FIG. 1, A1 128 drives M3 112, which is cascoded with M1 110. In this configuration, M1 110 and M3 112 form a source follower xe2x80x9cSF1xe2x80x9d 166, with an input signal provided by A1 128 at the gate terminal of M3 112, an output signal (not shown) produced at the source terminal of M3 112, and a current source provided by M1 110. Likewise, M2 118 and M4 120 form a source follower xe2x80x9cSF2xe2x80x9d 168; M5 114 and M7 116 form a source follower xe2x80x9cSF3xe2x80x9d 170; and M6 122 and M8 124 form a source follower xe2x80x9cSF4xe2x80x9d 172.
Thus, each gain boosting amplifier (e.g., A1 128, A2 132, A3 138, or A4 142) drives a capacitive-dominated load xe2x80x9cCloadxe2x80x9d, which can be expressed as shown in Eq. (6):
Cload=Cg(1xe2x88x92A),xe2x80x83xe2x80x83Eq. (6) 
where xe2x80x9cAxe2x80x9d is the gain of the corresponding source follower. A is defined as shown in Eq. (7):
A=vs/vg,xe2x80x83xe2x80x83Eq. (7) 
where xe2x80x9cvsxe2x80x9d is the small signal voltage at the source terminal of the driven MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122) and xe2x80x9cvgxe2x80x9d is the small signal voltage at the gate terminal of the driven MOSFET.
When the body terminal of the driven MOSFET is connected to a supply voltage (e.g., VDD 106 for a PMOSFET or VAG 108 for a NMOSFET), the gain A of each source follower can also be derived to be expressed as shown in Eq. (8):
A=gm/(gm+gmb).xe2x80x83xe2x80x83Eq. (8) 
This is due to the phenonemon of the xe2x80x9cMOSFET body effectxe2x80x9d in which the body-to-source voltage of a MOSFET acts to change its threshold voltage, and thereby change the drain current for a given gate-to-source voltage. The body effect gives rise to the body transconductance gmb, which can be derived to be expressed as shown in Eq. (9):
gmb=(xcex3xc3x97gm)/(VSB+2|xcfx86f|),xc2xdxe2x80x83xe2x80x83Eq. (9) 
where xe2x80x9cxcex3xe2x80x9d is the (process dependent) threshold voltage parameter, xe2x80x9cVSBxe2x80x9d is the large signal voltage potential between the source and body terminals, and xe2x80x9cxcfx86fxe2x80x9d is the Fermi potential of the junction. Eq. (8) demonstrates that a large value for body transconductance gmb reduces the value for gain A. This is undesirable. In state of the art CMOS digital processes, gmb for PMOSFETs can have a magnitude equal to 30 to 50 percent of gm. Thus, by application of Eq. (8), A can be as low as 0.65 to 0.75.
As noted above, because of the settling performance requirements of precision switched capacitor circuits, conventional gain boosted folded cascode operational amplifier 200 uses relatively large MOSFETs. Hence, the gate capacitance Cg of each driven MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122) can be fairly substantial. When the gain A of the corresponding source follower (e.g., SF1 166, SF2 168, SF3 170, or SF4 172) is low, the capacitive-dominated load Cload of the corresponding gain boosting amplifier (e.g., A1 128, A2 132, A3 138, or A4 142), by application of Eq. (6), remains significant. In order to carry this significant load, each gain boosting amplifier must consume a relatively large amount of power.
Furthermore, controlling the stability of each feedback network (e.g., FN1 130, FN2 134, FN3 140, or FN4 144) at high frequencies can be difficult because the capacitance at the source terminal of the driven MOSFET appears as a nondominant pole in the transfer function of the feedback network.
Returning to FIGS. 2A and 2B, conventionally, the MOSFET body effect can be eliminated by connecting body terminal 220 to source terminal 216, rather than to a supply voltage (e.g., VDD 106 ). However, while this approach removes the effect of the body transconductance gmb on the gain A of the corresponding source follower (and thus, by application of Eq. (6), reduces the capacitive-dominated load Cload of the corresponding gain boosting amplifier), it also connects the well-to-substrate capacitance CWell 366 to the source terminal 316. This has the effect of moving the nondominant pole in the transfer function to a lower frequency, which reduces the range of stable frequencies over which the feedback network can operate.
What is needed is a mechanism that mitigates the MOSFET body effect and reduces the effect of the well-to-substrate capacitance on the MOSFET.
The present invention relates to a biasing scheme that mitigates the MOSFET body effect and reduces the effect of the well-to-substrate capacitance on the MOSFET. More specifically, the present invention, at high frequencies, mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET, and reduces the power consumed by the gain boosting amplifier.
The present invention can be realized in any number of embodiments in which a circuit replicates the voltage at the source terminal of a MOSFET and applies this replicated voltage to the body terminal of the MOSFET. In this manner, the circuit mitigates the body effect of the MOSFET. The connection to the body terminal of the MOSFET forms a capacitive divider network at the body terminal that acts to reduce the effect of the body transconductance by a factor of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the MOSFET. Advantageously, this mitigates the effect of the well-to-substrate capacitance.
In an embodiment, the biasing scheme of the present invention can be realized by another MOSFET. The MOSFET and the other MOSFET are configured so that a voltage at the source terminal of the other MOSFET equals the voltage at the source terminal of the MOSFET. The source terminal of the other MOSFET is connected to the body terminal of the MOSFET.
In another embodiment, the biasing scheme of the present invention can be realized by an operational amplifier. The source terminal of the MOSFET is connected to the noninverting terminal of the operational amplifier and the output of the operational amplifier is connected to the inverting terminal of operational amplifier and to the body terminal of the MOSFET.
In yet another embodiment using an operational amplifier, the biasing scheme of the present invention can be realized by connecting the MOSFET to the operational amplifier to form a feedback network. The inverting terminal of the operational amplifier is connected to the source terminal of the MOSFET and the output of the operational amplifier is connected to the gate terminal of the MOSFET. A bias voltage is connected to the noninverting terminal of the operational amplifier.
In a related embodiment, the bias voltage is connected to the body terminal of the MOSFET. The bias voltage is produced by a biasing network. The biasing network includes a connection to the body terminal of the MOSFET that forms a capacitive divider network at the body terminal.
Alternatively, the bias voltage is replicated by an additional biasing network and the replicated bias voltage is connected to the body terminal of the MOSFET. The additional biasing network has a lower transconductance than the biasing network.
Advantageously, the biasing network or the additional biasing network reduces the capacitive load of the operational amplifier.
Advantageously, the biasing network or the additional biasing network improves the stability of the feedback network by contributing a negative half plane zero to the transfer function of the feedback network.
In an embodiment, the biasing scheme of the present invention can be used for a source follower. Advantageously, the biasing scheme of the present invention mitigates the reduction in gain of the source follower caused by the body effect of the driven MOSFET of the source follower.
In another embodiment, the biasing scheme of the present invention can be used for a gain boosted operational amplifier. In an alternative, the biasing scheme of the present invention is used for the driven PMOSFETs of the gain boosted operational amplifier. In another alternative, the biasing scheme of the present invention is used for the driven NMOSFETs of the gain boosted operational amplifier.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
FIG. 1 is a schematic diagram of an exemplary conventional gain boosted folded cascode operational amplifier 100.
FIG. 2A is a cutaway, cross sectional view of a conventionally fabricated PMOSFET 200.
FIG. 2B is a schematic diagram of a small signal model circuit 250 of PMOSFET 200.
FIG. 3 is a schematic diagram of an exemplary conventional biasing network 300 as would be used to support gain boosted folded cascode operational amplifier 100.
FIG. 4 is a schematic diagram of a representative gain boosted folded cascode operational amplifier 400 with the biasing scheme of the present invention.
FIG. 5 is a schematic diagram of a capacitive divider model 500 for a MOSFET biased in the manner of the present invention.
FIG. 6 is a schematic diagram of a small signal model 600 for a source follower.
FIG. 7 is a schematic diagram of conventional biasing network 300 with additional biasing network 700 of the present invention.
FIG. 8 is a Bode plot of a simulated response of gain boosted folded cascode operational amplifier 400 biased in the manner of the present invention.
FIG. 9 is a Bode plot of a simulated response of a gain boosting amplifier (e.g., A1 128, A2 132, A3 138, or A4 142) driving a MOSFET (e.g., M3 112, M4 120, M5 114, or M6 122) biased in the manner of the present invention.
FIG. 10A is a schematic diagram of an embodiment 1000 of the present invention to bias a MOSFET 1002.
FIG. 10B is a schematic diagram of an alternative embodiment 1006 of the present invention to bias MOSFET 1002.
FIG. 11 shows a flow chart of a method 1100 for biasing a MOSFET.
FIG. 12 shows a flow chart of a method 1200 for controlling the voltage of the source terminal of the MOSFET.